<dec f='src/src/sys/arch/x86/include/cacheinfo.h' l='11' type='u_int'/>
<offset>64</offset>
<doc f='src/src/sys/arch/x86/include/cacheinfo.h' l='11'>/*
					 * or page size for TLB,
					 * or prefetch size
					 */</doc>
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<use f='src/src/sys/arch/x86/x86/identcpu.c' l='239' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='244' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='250' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='255' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='260' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='265' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='280' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='297' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='316' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='321' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='326' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='331' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='586' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='591' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='596' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='605' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='625' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='629' u='w' c='cpu_probe_c3'/>
