<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/include/core/gpuobj.h' l='19' type='struct nouveau_mm_node *'/>
<offset>320</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='47' u='r' c='nouveau_gpuobj_destroy'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='49' u='a' c='nouveau_gpuobj_destroy'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='124' u='a' c='nouveau_gpuobj_create_'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='128' u='r' c='nouveau_gpuobj_create_'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='195' u='r' c='_nouveau_gpuobj_rd32'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='196' u='r' c='_nouveau_gpuobj_rd32'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='205' u='r' c='_nouveau_gpuobj_wr32'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_gpuobj.c' l='206' u='r' c='_nouveau_gpuobj_wr32'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_namedb.c' l='83' u='r' c='nouveau_namedb_lookup_cinst'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/core/nouveau_core_namedb.c' l='84' u='r' c='nouveau_namedb_lookup_cinst'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='114' u='r' c='nv50_disp_dmac_object_attach'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='61' u='r' c='nvd0_disp_dmac_object_attach'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv50.c' l='173' u='r' c='nv50_fifo_object_attach'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv50.c' l='237' u='r' c='nv50_fifo_chan_ctor_dma'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv50.c' l='244' u='r' c='nv50_fifo_chan_ctor_dma'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv50.c' l='290' u='r' c='nv50_fifo_chan_ctor_ind'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv50.c' l='298' u='r' c='nv50_fifo_chan_ctor_ind'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv84.c' l='139' u='r' c='nv84_fifo_object_attach'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv84.c' l='210' u='r' c='nv84_fifo_chan_ctor_dma'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv84.c' l='217' u='r' c='nv84_fifo_chan_ctor_dma'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv84.c' l='272' u='r' c='nv84_fifo_chan_ctor_ind'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/nouveau_engine_fifo_nv84.c' l='280' u='r' c='nv84_fifo_chan_ctor_ind'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/software/nouveau_engine_software_nv50.c' l='63' u='r' c='nv50_software_mthd_dma_vblsem'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bar/nouveau_subdev_bar_nv50.c' l='255' u='r' c='nv50_bar_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bar/nouveau_subdev_bar_nv50.c' l='256' u='r' c='nv50_bar_init'/>
