<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_drv.h' l='925' type='void intel_update_fbc(struct drm_device * dev)'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='2554' u='c' c='intel_pipe_set_base'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3749' u='c' c='ironlake_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3790' u='c' c='haswell_crtc_enable_planes'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3985' u='c' c='ironlake_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4032' u='c' c='haswell_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4424' u='c' c='valleyview_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4469' u='c' c='i9xx_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4534' u='c' c='i9xx_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8573' u='c' c='intel_unpin_work_fn'/>
<def f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='468' ll='631' type='void intel_update_fbc(struct drm_device * dev)'/>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='449'>/**
 * intel_update_fbc - enable/disable FBC as needed
 * @dev: the drm_device
 *
 * Set up the framebuffer compression hardware at mode set time.  We
 * enable it if possible:
 *   - plane A only (on pre-965)
 *   - no pixel mulitply/line duplication
 *   - no alpha buffer discard
 *   - no dual wide
 *   - framebuffer &lt;= max_hdisplay in width, max_vdisplay in height
 *
 * We can&apos;t assume that any compression will take place (worst case),
 * so the compressed buffer has to be the same size as the uncompressed
 * one.  It also must reside (along with the line length buffer) in
 * stolen memory.
 *
 * We need to enable/disable FBC on a global basis.
 */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sprite.c' l='549' u='c' c='intel_enable_primary'/>
