1024 /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 ATOM_DEVICE_DFP1_SUPPORT 0x0008 ATOM_DEVICE_DFP6_SUPPORT 0x0040 ATOM_DEVICE_DFP2_SUPPORT 0x0080 ATOM_DEVICE_DFP3_SUPPORT 0x0200 ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 ulOtherDisplayMisc: Other display related flags, not defined yet. ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[3]=0: Enable HW AUX mode detection logic =1: Disable HW AUX mode dettion logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State usNBP1Voltage: VID for voltage on NB P1 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set to indicate a range. SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) **********************************************************************************************************************/ // this Table is used for Liano/Ontario APU