SC(4)

NAME
sc - Sun Sun-2 SCSI bus host adaptor driver

SYNOPSIS

  sun2
sc0 at mbmem0 addr 0x80000 ipl 2
sc1 at mbmem0 addr 0x84000 ipl 2

  sun2 and sun4
sc0 at vme0 addr 0x200000 irq 2 vec 0x40

DESCRIPTION
The sc driver provides support for the Sun Microsystems "Sun-2" SCSI Bus Controller chipset found on various VME boards (Sun part #s 501-1045, 501-1138, 501-1149, and 501-1167) and on the "Sun-2 SCSI/Serial" (Sun part # 501-1006) Multibus board.

All versions of this driver can be configured with a flags directive in the config(1) file. The values are bits in a bitfield, and are interpreted as follows:

0x0ff
    Set bit (1<<target) to disable SCSI parity checking
0x100
    Set this bit to disable DMA interrupts (poll)
0x200
    Set this bit to disable DMA entirely (use PIO)

For example: "flags 0x1ff" would disable DMA interrupts, and disable parity checking for targets 0-7. The "target" is the SCSI ID number of a particular device on a particular SCSI bus.

SEE ALSO
cd(4), ch(4), intro(4), scsi(4), sd(4), st(4)

AUTHORS
Matt Fredette <fredette@NetBSD.org>, David Jones, Gordon Ross <gwr@NetBSD.org>, Adam Glass <glass@NetBSD.org>, Jason R. Thorpe <thorpej@NetBSD.org>.

BUGS
This SCSI chipset is rumored to have bugs in its handling of SCSI parity, therefore it is recommended that you disable parity on all SCSI devices connected to this controller, and configure it with a 0x0ff value for its flags directive in the config(1) file.

This chipset has no support for raising the ATN signal, so there is no way to ever schedule a MSG_OUT phase on the bus. Currently, the driver will ultimately reset the bus if this phase is ever requested by the upper layer SCSI driver.

This chipset has no support for SCSI disconnect/reselect. This means that slow devices, such as tape drives, can hog, or "lock up" the SCSI bus.

This driver has not been tested in combination with non-SCSI devices behind Emulex or Adaptec bridges, which are common in Sun 2s and in Sun Shoebox-type configurations. These devices pre-date the SCSI-I spec, and might not behave the way the chipset code currently expects.